A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal

Manuscript received June 16, 1999. Manuscript revised August 14, 1999. † The authors are with the Department of Electrical Engineering, Science University of Tokyo, Noda-shi, 278-8510 Japan. SUMMARY A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably. key words: analog signal processing, MOS analog circuit, phase compensation, low impedance